To provide higher device packing density and reduced chip size for metal oxide semiconductor field effect transistor (MOSFET) integrated circuits, a number of design rules have been developed to alleviate alignment error problems between different interconnect layers. These design rules provide sufficient tolerance to mask misalignment and other process variations so that integrated circuits can be reliably manufactured.
Two design rules relate to forming a self-aligned contact (SAC) and a local interconnect (LI). These design rules are commonly used for memories, including DRAMs and SRAMs. Self-aligned contact as used herein refers generally to a source or drain contact which is formed such that it may overlap an adjacent gate. The overlap is permissible because the self-aligned contact is formed in a manner which provides additional isolation between the contact and the gate so that shorting is prevented. Local interconnect refers generally to any interconnection between elements of a semiconductor device, such as an interconnection between a gate, source or drain of one transistor and a gate, source or drain of another transistor in the same device.
However, a self-aligned contact and a local interconnect cannot be formed at the same time. This is primarily due to a difference in the etch selectivity required when etching through an overlying dielectric layer to a transistor source/drain region versus a transistor gate. The offset height between the transistor source/drain region and the transistor gate results in the use of separate masking steps. One additional mask is required for the self-aligned contact, and one additional mask is required for the local interconnect. Thus, two additional masks and masking steps are required to form both the self-aligned contact and the local interconnect in a semiconductor device.